This invention relates to an integrated circuit chip including a Hall element, and more particularly to an integrated circuit Hall element having a surrounding barrier that buffers chip stresses that reduce certain process dependent factors which tend to distort Hall element symmetry and contribute to the Hall element offset voltage.
Integrated circuits including Hall elements are well known. In a silicon integrated circuit the Hall element has a low sensitivity, and other portions of the IC usually contain a differential amplifier for amplifying the low value output voltage from the two sensing or output contacts of the Hall element. For example in the patent to Anselmo and Genesi U.S. Pat. No.3,816,766 issued June 11, 1974, and in the patent to Macdougall U.S. Pat. No. 4,253,107 issued February 24, 1981, both assigned to the same assignee as the present invention, such integrated circuits containing Hall elements are described in detail.
The Hall element output voltage is used as a measure of the ambient magnetic field. For example, a magnet is mounted to the integrated circuit whose output is responsive to the presence of or movement of a ferromagnetic body. Such a proximity detector is described by Avery in U.S. Pat. No. 4,443,716 issued April 17, 1984 and also assigned to the same assignee.
The reduction and control of the Hall element offset voltage has been the object of much attention, and especially the silicon integrated circuit Hall element that is followed by an on-board differential amplifier. It has been found that symmetry in the Hall element is fundamentally essential in order to provide a low offset voltage. An operating symmetry can be achieved by constructing a Hall element of an array of Hall cells that are arranged to have radially directed exciting currents with cell output voltages connected in parallel. Even when a Hall element has such symmetry, there often remains a troublesome offset voltage whose origin is not known or controllable.
It is therefore an object of the present invention to provide an integrated circuit including a Hall element having a unique structural barrier to built in chip stresses.
It is a further object of this invention to provide such an integrated circuit that has a Hall element whose offset voltage is less influenced by the layout of surrounding components and by process variables.